1. Field of the Invention
The present invention relates to digital circuits and more particularly to (ATD) Address Transition Detection circuits.
2. Description of Related Art
ATD circuits are employed in memory devices to detect a change in any one of the address lines of memory. When a new address is supplied by the user to memory, that address is received by both a memory controller and by the row and column decoders for the memory array. As the address transition is detected by the memory device, a new address has been supplied by the user, and this address must be decoded by the decoding circuitry of the memory device in order to access the actual memory address. When a memory address is to be accessed, the data path to and from the memory address must be precharged in preparation for the transfer of this data. This precharging may involve charging a capacitor in a row and column to be addressed. Typically, a pulse from the ATD circuit is used in the memory to begin precharging this path.
A device for precharging a memory circuit in response to an ATD circuits is disclosed in U.S. Pat. No. 5,493,538, issued on Feb. 20, 1996, and entitled Minimum Pulse Width Address Transition Detection Circuit, which is herein incorporated by reference. This patent discloses a device for detecting a change of address and latching the change for a period of time sufficient to precharge a memory. The address changes are detected by an edge detect and output as a series of pulses to the set input of a latch. Provided the latch has been reset before a pulse is received, the output of the latch will transition to a set condition. The set condition initiates memory precharge. The set condition also initiates a delayed feedback to the reset input of the latch. Precharge continues until the latch is reset. The problem with this device, however, is that when pulses are spaced apart in time by an interval less than the maximum delay interval, the pulse immediately after a pulse that placed the latch output in a set condition, will not be operated on. The '538 device will not therefore precharge memory for a sufficient period of time. This can lead to the need to resend an address in order to properly precharge memory. It can also lead to incorrect data being written to or read from memory if the memory has not been adequately precharged. The shortcomings of the '538 device are compounded in memories having address buses with a large number of address lines. In this environment the occurrence of narrowly spaced address changes is relatively frequent and the inability of the '538 device to detect each pulse results in delayed or incorrect memory accesses.
In memory applications, the ATD pulse is also used to pre bias the sense amplifier, to boost the wordlines, or to precharge the output driver.
If the ATD does not detect each narrowly spaced address change, it may lead to delayed or incorrect memory accesses in the above application. For example, if two address transitions are narrowly spaced and only first address transitions are detected, the memory control circuit will not bias the sense amplifier to the optimized timing corresponding to the second address change since its address transition is not detected.
In the event the ATD circuit is used to boast or wordline, a specified time interval must exist between the final address transition and the boost of the wordlines. Otherwise, the wordlines may be boosted before the decoded wordlines have settled to their final state. This may cause the wrong set of wordlines to be boosted and can also lead to incorrect data being read from the memory. What is needed is an ATD circuit that will detect each address transition under all conditions.